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1 standard products UT54ACS164646S schmitt cmos 16-bit bidi rectional multipurpose registered transceiver datasheet may 17, 2012 www.aeroflex.com/16bitlogic features ? flexible voltage operation - 5v bus to 3.3v bus - 3.3v bus to 5v bus - 5v bus to 5v bus - 3.3v bus to 3.3v bus ? independent registers for a and b buses ? multiplexed real- time and stored data ? flow-through architect ure optimizes pcb layout ? cold- and warm-sparing - 750k ? minimum input impedance power-off - guranteed output tri-state wh ile one power supply is "off" and the other is "on" ? schmitt trigger inputs to filter noisy signals ? all inputs are 5v tolerant regardless of power supply voltage ? ???? m crh cmos technology ? operational environment: - total dose: 100k rad(si) - single event latchup immune>110 mev-cm 2 /mg - seu onset let >75 mev-cm 2 /mg ? high speed, low power consumption ? available qml q or v processes ? ? standard microcircuit drawing: 5962-06234 ? package: - 56-pin ceramic flatpack pin description description the UT54ACS164646S is a 16-bit, multipurpose, registered, level shifting, bus transceiver consisting of d-type flip-flops, control circuitry, and 3-state outputs arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. the high-speed, low power UT54ACS164646S transceiver is designed to perform multi- ple functions including: asynchronous two-way communica- tion, signal buffering, voltage translation, cold- and warm- sparing. the device can be us ed as two independant 8-bit transceivers or one 16-bit transceiver. data on the a or b bus is clocked into the registers on the rising edge of the appropri- ate clock (xclkab or xclkba ) input. with either v dd sup- ply equal to zero volts, the UT54ACS164646S outputs and inputs present a minimum impedance of 750k ? making it ideal for ?cold-spare? and "warm-spare" applications. by vir- tue of its flexible powe r supply interface, the UT54ACS164646S may operate as a 3.3-volt only, 5-volt only, or mixed 3.3v/5v bus transceiver. the output-enable (xoe ) and direction-control (xdir) inputs are provided to control the tri-state function and input/output direction of the transceiver resp ectively. the select controls (xsab and xsba) select whether st ored register data or real- time data is driven to the outputs as determined by the xdir inputs. the circuitry used for se lect control eliminates the typ- ical decoding glitch that occu rs in a multiplexer during the transition between stored and real -time data. regardless of the selected operating mode ("real- time" or "recall"), a rising edge on the port input clocks (xclkab and xclkba) will latch the corresponding i/o states into their respective registers. furthermore, when a data port is isolated (xoe = high), a-port data may be stored into its co rresponding register while b-port data may be independantly stored into its corresponding regis- ters. therefore, when an output function is disabled, the input function is still enabled and may be used to store and transmit data. lastly, only one of the two buses, xa-port or xb-port, may be driven at a time. pin names description xoe output enable input (active low) xdir direction control inputs xax side a inputs or 3-state outputs (3.3v port) xbx side b inputs or 3-state outputs (5v port) xsab select real-time or stored a bus data to b bus xsba select real-time or stored b bus data to a bus xclkab store a bus data xclkba store b bus data
2 56-lead flatpack pinout logic symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 1dir 1clkba 1sba vss 1b1 1b2 vddb 1b3 1b4 1b5 vss 1b6 1b7 1b8 2b1 2b2 2b3 vss 2b4 2b5 2b6 vddb 2b7 2b8 vss 2sba 2clkba 2dir 1oe 1clkab 1sab vss 1a1 1a2 vdda 1a3 1a4 1a5 vss 1a6 1a7 1a8 2a1 2a2 2a3 vss 2a4 2a5 2a6 vdda 2a7 2a8 vss 2sab 2clkab 2oe g3 6 1b2 8 49 48 1a2 1b3 9 1b4 10 1b5 12 1b6 1a3 45 1a6 47 1a5 51 1a4 13 1b7 14 1b8 43 1a8 44 1a7 1 1dir 3 en1 (ba) 3 en2 (ab) 56 1oe 16 2b2 17 2b3 19 2b4 20 2b5 21 2b6 23 2b7 24 2b8 40 2a2 2a3 36 2a6 37 2a5 38 2a4 33 2a8 34 2a7 41 1clkab 1sab 1clkba 55 54 2 3 29 1sba 2oe 28 2dir c4 g5 c6 g7 10 en8 (ba) 30 31 27 26 2clkab 2sab 2clkba 2sba 10 en9 (ab) g12 g14 c11 c13 g10 > 1 5 4d 1 5 > 1 6d 7 7 1 2 1b1 > 1 12 11d 1 12 > 1 13d 14 14 1 9 2b1 5 8 2a1 1 1a1 52 42 15
3 power table i/o guidelines control signals xdir, xoe, xsab, xsba, xclkab, and xclkba are powered by v dda . all inputs are 5-volt tolerant. when vdd2 is at 3.3 volts, either 3.3 or 5-volt cmos logic levels can be applied to all control inputs. control signals dirx, /oex, xsab, xsba, xclkab, and xclkba are pow- ered by vdda. all inputs are 5-volt tolerant. additionally, it is recommended that all unused inputs be tied to vss through a 1k ? to 10k ? resistor. it's good design practice to tie the un- used input to vss via a resistor to reduce noise susceptibility. the resistor protects the input pin by limiting the current from high going variations in vss. the number of inputs that can be tied to the resistor pull-down can vary. it is up to the system de- signer to choose how many inputs are tied together by figuring out the max load the part can drive while still meeting system performance specs. input signal tr ansitions should be driven to the device with a rise and fall time that is <100ms. function table power application guidelines for proper operation connect power to all v ddx pins and ground all v ss pins (i.e., no floating v ddx or v ss input pins). by virtue of the UT54ACS164646S warm-spare feature, power supplies v ddb and v dda may be applied to the device in any order. to ensure the device is in cold-spare mode, both sup- plies, v ddb and v dda , must be equal to v ss +/- 0.3v. warm- spare operation is in effect when one power supply is >1v and the other power supply is equal to v ss +/- 0.3v. if v ddb has a power-on ramp rate longer than 1 second, then v dda should be powered-on first to ensure proper control of xdir and xoe . during normal operation of the part, after power-up, ensure v ddb > v dda . by definition, warm sparing occurs when half of the chip re- ceives its normal vdd supply value while the vdd supplying the other half of the chip is set to 0.0v. when the chip is ?warm spared?, the side that has its vdd set to a normal operational value is ?actively? tristated becau se the chip?s internal oe sig- nal is forced low. the side of the chip that has vdd set to 0.0v is ?passively? tristated by the cold spare circuitry. in order to minimize transients and current consumption, the user is encouraged to first apply a high level to the xoe pins and then power down the appropriate supply. + the data-output functions may be enable d or disabled by various signals xoe or xdir. data-input functions are always en abled, i.e. data at the bus terminals is stored on every low- to-high transition of the clock inputs. port b port a operation 5 volts 3.3 volts voltage translator 5 volts 5 volts non translating 3.3 volts 3.3 volts non translating v ss v ss cold spare v ss 3.3v or 5v port a warm spare 3.3v or 5v v ss port b warm spare inputs data i/o + operation or function xoe xdir xclkab xclkba xsab xsba xa1-xa8 xb1-xb8 xx ? x x x input unspecified store a, b unspecified + xx x ? x x unspecified input store b, a unspecified + hx ?? x x input input store a and b data + h x h or l h or l x x input input isolation, hold storage l l x x x l output input real-time b data to a bus l l x h or l x h output input recall stored b data to a bus l h x x l x input output real-time a data to b bus l h h or l x h x input output recall stored a data to b bus
4 logic diagram 1clkab 1clkba 2clkab 2clkba a b y sel enb oe2 29 dir2 2sab 2sba 2b1 28 30 31 27 26 15 d clk q enb b a y sel d clk q 2a1 42 seven channels identical to channel one above 2b2 16 2b3 17 2b4 19 2b5 20 2b6 21 2b7 23 24 2b8 2a2 41 2a3 40 2a4 38 2a5 37 2a6 36 2a7 34 33 2a8 a b y sel enb oe1 56 dir1 1sab 1sba 1b1 1 55 54 2 3 5 d clk q enb b a y sel d clk q 1a1 52 seven channels identical to channel one above 1b2 6 1b3 8 1b4 9 1b5 10 1b6 12 1b7 13 14 1b8 1a2 51 1a3 49 1a4 48 1a5 47 1a6 45 1a7 44 43 1a8
5 operational environment 1 notes: 1. logic will not latchup during radiation ex posure within the limits defined in the table. 2. adams 90% worst case particle environment, geosynchronous orbit, 100mils of aluminum shielding 3. not tested, inherent of cmos technology. 4. core logic is driven by v ddb . absolute maximum ratings 1 note: 1. stresses outside the listed absolute maxi mum ratings may cause permanen t damage to the device. this is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the opera tional sections is not recommend ed. exposure to absolute maxi mum rating conditio ns for extended periods may affect device reliability and performance. 2. for cold spare mode (v ddx = v ss +/- 0.3v), v i/ox may be -0.3v to the maximum recommended operating v ddx + 0.3v. parameter limit units total dose 1.0e5 rad(si) sel let threshold >110 mev-cm 2 /mg seu onset let threshold 4 >97 @4.5v, >74@ 3.0v mev-cm 2 /mg seu error rate 2 immune @4.5v, 6.3e-10 @3.0v errors/bit-day neutron fluence 3 1.0e14 n/cm 2 symbol parameter limit (mil only) units v i/ob (port b) 2 voltage any pin -0.3 to 6.0 v v i/oa (port a) 2 voltage any pin -0.3 to 6.0 v v ddb supply voltage -0.3 to 6.0 v v dda supply voltage -0.3 to 6.0 v t stg storage temperature range -65 to +150 ? c t j maximum junction temperature +175 ? c ? jc thermal resistance junction to case 20 ? c/w i i dc input current ? 10 ma p d maximum power dissipation 250 mw
6 dual supply operating conditions note: 1. during normal operation, v ddb > v dda . 2. all input pins are 5-volt to lerant inputs powered by v dda . therefore, when v dda is at 3.3 volts, either 3.3 or 5-volt cmos logic levels can be applied to all control inputs. symbol parameter limit units v ddb 1 supply voltage 3.0 to 3.6 or 4.5 to 5.5 v v dda 1 supply voltage 3.0 to 3.6 or 4.5 to 5.5 v v inb (port b) 2 input voltage any pin 0 to v ddb v v ina (port a) 2 input voltage any pin 0 to v dda v t c temperature range -55 to +125 ? c
7 dc electrical characteristics 1 (t c = -55 ? c to +125 ? c); unless otherwise noted, tc is per the temperature ordered. symbol parameter condition min max unit v t + schmitt trigger, positive going threshold 2 v ddx from 3.0v to 5.5v .7v ddx v v t - schmitt trigger, negative going threshold 2 v ddx from 3.0v to 5.5v .3v ddx v v h1 schmitt trigger range of hysteresis v ddx from 4.5v to 5.5v 0.7 v v h2 schmitt trigger range of hysteresis v ddx from 3.0v to 3.6v 0.5 v i in input leakage current v ddx from 3.6v to 5.5v v in = v ddx or v ss -1 1 ? a i oz three-state output leakage current v ddx from 3.6 to 5.5 v in = v ddx or v ss -1 1 ? a i cs cold sparing input leakage current 3 (any pin) v in = 5.5v v ddb = v dda = v ss -5 7 ? a i ws warm sparing input leakage current 3 (any pin) v in = 5.5; v dda = 3v to 5.5v & v ddb = v ss or v ddb = 3v to 5.5v & v dda = v ss -3 3 ? a i os1 short-circuit output current 6, 10 v o = v ddx or v ss v ddx from 4.5 to 5.5 -200 200 ma i os2 short-circuit output current 6, 10 v o = v ddx or v ss v ddx from 3.0 to 3.6 -100 100 ma v ol1 low-level output voltage 4 v ddx = 4.5v; i ol = 8ma 0.4 v v ddx = 4.5v; i ol = 100 ? a0.2 v ol2 low-level output voltage 4 v ddx = 4.5v -55 ? c, 25 ? c i ol = 12ma +125 ? c 0.4 0.55 v v ol3 low-level output voltage 4 v ddx = 3.0v; i ol = 8ma 0.5 v v ddx = 3.0v; i ol = 100 ? a0.2v v ol4 low-level output voltage 4 v ddx = 3.0v -55 ? c, 25 ? c i ol = 12ma +125 ? c 0.5 0.6 v v
8 notes: * for devices procured with a total ionizing dose tolerance guar antee, the post-irrad iation performance is guaranteed at 25c p er mil-std-883 method 1019, condition a up to the maximum tid level procured. 1. all specifications valid for radiation dose ? 1e5 rad(si) per mil-std-883, method 1019. 2. functional tests are conducted in accordance with mil-std-883 with th e following input test conditions: v ih = v ih (min) + 20%, - 0%; v il = v il (max) + 0%, - 50%, as specified herein, for ttl, cmos, or schmitt compatible inputs. devices may be tested using any input voltage within the above specified range, but are guaranteed to v ih (min) and v il (max). 3. this parameter is uneffected by the state of x oe or xdir. 4. per mil-prf-38535, for current density ? 5.0e5 amps/cm 2 , the maximum product of load cap acitance (per output buffer) times frequency should not exceed 3,765 pf-mhz. 5. guaranteed by characterization. 6. not more than one output may be shorted at a time for maximum duration of one second. 7. power does not include power contri bution of any cmos output sink current. 8. power dissipation specifi ed per switching output. 9.capacitance measured for initial qualification and wh en design changes may affect the valu e. capacitance is measured between the designated terminal and v ss at frequency of 1mhz and a signal amplitude of 50 mv rms maximum. 10. supplied as a design limit, but not guaranteed or tested. v oh1 high-level output voltage 4 v ddx = 4.5v; i oh = -8ma v ddx - 0.5 v v ddx = 4.5v; i oh = -100 ? av ddx - 0.2 v oh2 high-level output voltage 4 v ddx = 4.5v -55 ? c, 25 ? c i ol = -12ma +125 ? c v ddx - 0.6 v ddx - 0.7 v v v oh3 high-level output voltage 4 v ddx = 3.0v; i oh = -8ma v ddx - 0.6 v v ddx = 3.0v; i oh = -100 ? av ddx - 0.2 v oh4 high-level output voltage 4 v ddx = 3 . 0 v - 5 5 ? c, 25 ? c i ol = -12ma +125 ? c v ddx - 0.8 v ddx - 0.95 v v p total1 power dissipation 5,7, 8 c l = 20pf v ddb = v dda = 4.5v to 5.5v 2.0 mw/ mhz p total2 power dissipation 5, 7, 8 c l = 20pf v ddb = v dda = 3.0v to 3.6v 1.5 mw/ mhz i ddq standby supply current v ddb or v dda pre-rad 25 o c v in = v ddx or v ss v ddb = v dda = 5.5v xoe = v dda 10 ? a standby supply current v ddb or v dda pre-rad -55 o c, +125 o c 100 standby supply current v ddb or v dda post-rad 25 o c 100 c in input capacitance 9 ? = 1mhz v ddx from 3.0v to 5.5v 15 pf c out output capacitance 9 ? = 1mhz v ddx from 3.0v to 5.5v 15 pf symbol parameter condition min max unit
9 ac electrical characteristics* 1 (port b = 5 volt, port a = 3.3 volt) (v ddb = 5v ? 10%; v dda = 3.3v ? 0.3v); unless otherwise noted, tc is per the temperature ordered. notes: * for devices procured with a total ionizing dose tolerance gua rantee, the post-irradiation perf ormance is guaranteed at 25 o c per mil-std-883 me thod 1019, condition a up to the maximum tid level procured. 1. all specifications valid for radiation dose ? 1e5 rads(si) per mil-std-883, method 1019. 2. these parameters are measured with th e internal output state of the storage regi ster opposite to th at of the bus input. 3. xdir to bus times are guaranteed by design, but not tested. xoe to bus times are tested. 4. output skew is defined as a comparison of any two output tran sitions of the same type at th e saame temperature and voltage f or the same port within the same byte: 1a1 through 1a8 are compared high-to-low versus high-to-low an d low-to-high versus low-to-high; similarly 1b1 through 1b8 are compared, 2a1 through 2a8 are compared, and 2b1 th rough 2b8 are compared. 5. differential output skew is defined as a comparison of any tw o output transitions of opposite types on the same type at the same temperature and voltage for the same port within the same byte: 1a1 through 1a8 are compared high-to-low versus low-to-high; similarly 1b1 through 1b8 are com pared, 2a1 through 2a8 are compared, and 2b1 thro ugh 2b8 are compared. 6. guaranteed by character ization, but not tested. symbol parameter minimum maximum unit t plh1 propagation delay data to bus 3.5 9 ns t phl1 propagation delay data to bus 3.5 9 ns t plh2 xclkab ?? or xclkba ?? to bus ? 4.5 10.5 ns t phl2 xclkab ?? or xclkb ?? to bus ? 4.5 10.5 ns t plh3 2 xsab ?? or xsba ? to bus 4 10.5 ns t phl3 2 xsab ?? or xsba ? to bus 4 10.5 ns t plh4 2 xsba ??? or xsab ???? to bus 4 10.5 ns t phl4 2 xsba ??? or xsab ???? to bus 4 10.5 ns t pzh1 output enable time xoe to bus 4 10 ns t pzl1 output enable time xoe to bus 4 10 ns t plz1 output disable time xoe to bus high impedance 3 10 ns t phz1 output disable time xoe to bus high impedance 3 10 ns t pzh2 3 output enable time xdir to bus 3 12 ns t pzl2 3 output enable time xdir to bus 3 12 ns t plz2 3 output disable time xdir to bus high impedance 3 12 ns t phz2 3 output disable time xdir to bus high impedance 3 12 ns t skew 4 skew between outputs 800 ps t ost 5 dfiferential skew between outputs 1500 ps t part 6 part to part skew 500 ps ? ? ? ?
10 t plzn t pzhn t pzln t phln t phzn propagation delay input output v ddx v ddx /2 0v t plhn v oh v ol control input 5v output normally low enable disable times 5v output normally high v dda v dda /2 0v v ddb /2 v ddb /2 .8v ddb .2v ddb v ddx /2+0.2 v ddx /2-0.2 .2v ddx + .2v .8v ddx - .2v t plzn t pzhn t pzln t phzn 3.3v output normally low 3.3v output normally high v dda /2 v dda /2 .7v dda .2v dda v ddx /2+0.2 v ddx /2-0.2 .2v ddx + .2v .7v ddx - .2v 0.5v ddx + 0.2 enable disable times ac timing waveforms for level translation (e.g. v dda = 3.3v +/- 0.3v and v ddb = 5v +/- 10%) 0.5v ddx - 0.2
11 ac electrical characteristics* 1 (port a = port b, 5 volt operation) (v ddb = 5v ? 10%; v dda = 5v + 10%) (t c = -55 ? c to +125 ? c) ; unless otherwise noted, tc is per the temperature ordered notes: * for devices procured with a total ionizing dose tolerance gua rantee, the post-irradiation perf ormance is guaranteed at 25 o c per mil-std-883 me thod 1019, condition a up to the maximum tid level procured. 1. all specifications valid for radiation dose ? 1e5 rads(si) per mil-std-883, method 1019. 2. these parameters are measured with th e internal output state of the storage regi ster opposite to th at of the bus input. 3. xdir to bus times are guaranteed by design, but not tested. xoe to bus times are tested. 4. output skew is defined as a comparison of any two output tran sitions of the same type at th e saame temperature and voltage f or the same port within the same byte: 1a1 through 1a8 are compared high-to-low versus high-to-low an d low-to-high versus low-to-high; similarly 1b1 through 1b8 are compared, 2a1 through 2a8 are compared, and 2b1 th rough 2b8 are compared. 5. differential output skew is defined as a comparison of any tw o output transitions of opposite types on the same type at the same temperature and voltage for the same port within the same byte: 1a1 through 1a8 are compared high-to-low versus low-to-high; similarly 1b1 through 1b8 are com pared, 2a1 through 2a8 are compared, and 2b1 thro ugh 2b8 are compared. 6. guaranteed by character ization, but not tested. symbol parameter minimum maximum unit t plh1 propagation delay data to bus 3.5 7.5 ns t phl1 propagation delay data to bus 3.5 7.5 ns t plh2 xclkab ?? or xclkba ?? to bus 4 9 ns t phl2 xclkab ?? or xclkba ?? to bus 4 9 ns t plh3 2 xsab ?? or xsba ? to bus 3 8 ns t phl3 2 xsab ?? or xsba ? to bus 3 8 ns t plh4 2 xsba or xsab to bus 3 8 ns t phl4 2 xsba or xsab to bus 3 8 ns t pzh1 output enable time xoe to bus 3.5 9 ns t pzl1 output enable time xoe to bus 3.5 9 ns t plz1 output disable time xoe to bus high impedance 3 8 ns t phz1 output disable time xoe to bus high impedance 3 8 ns t pzh2 3 output enable time xdir to bus 3 11 ns t pzl2 3 output enable time xdir to bus 3 11 ns t plz2 3 output disable time xdir to bus high impedance 3 11 ns t phz2 3 output disable time xdir to bus high impedance 3 11 ns t skew 4 skew between outputs 600 ps t ost 5 differential output skew 1500 ps t part 6 part to part skew 500 ps ?? ?? ?? ??
12 t plzn t pzhn t pzln t phzn control input 5v output normally low enable disable times 5v output normally high v ddx v ddx /2 0v v ddx /2 v ddx /2 .8v ddx .2v ddx v ddx /2+0.2 v ddx /2-0.2 .2v ddx + .2v .8v ddx - .2v t phln propagation delay input output v ddx v ddx /2 0v t plhn ac timing waveform s for 5-volt only operation (e.g. v dda = v ddb = 5v +/- 10%) v oh v ol 0.5v ddx + 0.2 0.5v ddx - 0.2
13 ac electrical characteristics* 1 (port a = port b, 3.3 volt operation) (v ddb = v dda = 3.3v ? 0.3v) (t c = -55 ? c to +125 ? c); unless otherwise noted, tc is per the temperature ordered notes: * for devices procured with a total ionizing dose tolerance gua rantee, the post-irradiation perf ormance is guaranteed at 25 o c per mil-std-883 me thod 1019, condition a up to the maximum tid level procured. 1. all specifications valid for radiation dose ? 1e5 rads(si) per mil-std-883, method 1019. 2. these parameters are measured with th e internal output state of the storage regi ster opposite to th at of the bus input. 3. xdir to bus times are guaranteed by design, but not tested. xoe to bus times are tested. 4. output skew is defined as a comparison of any two output tran sitions of the same type at th e saame temperature and voltage f or the same port within the same byte: 1a1 through 1a8 are compared high-to-low versus high-to-low an d low-to-high versus low-to-high; similarly 1b1 through 1b8 are compared, 2a1 through 2a8 are compared, and 2b1 th rough 2b8 are compared. 5. differential output skew is defined as a comparison of any tw o output transitions of opposite types on the same type at the same temperature and voltage for the same port within the same byte: 1a1 through 1a8 are compared high-to-low versus low-to-high; similarly 1b1 through 1b8 are com pared, 2a1 through 2a8 are compared, and 2b1 thro ugh 2b8 are compared. 6. guaranteed by character ization, but not tested. symbol parameter minimum maximum unit t plh1 propagation delay data to bus 4 10 ns t phl1 propagation delay data to bus 4 10 ns t plh2 xclkab ?? or xclkba ?? to bus 4.5 12.5 ns t ph2 xclkab ?? or xclkba ?? to bus 4.5 12.5 ns t plh3 2 xsab ?? or xsba ? to bus 4.5 11 ns t phl3 2 xsab ?? or xsba ? to bus 4.5 11 ns t plh4 2 xsba or xsab to bus 4.5 11 ns t phl4 2 xsba or xsab to bus 4.5 11 ns t pzh1 output enable time xoe to bus 4 11 ns t pzl1 output enable time xoe to bus 4 11 ns t plz1 output disable time xoe to bus high impedance 4 10 ns t phz1 output disable time xoe to bus high impedance 4 10 ns t pzh2 3 output enable time xdir to bus 3 13 ns t pzl2 3 output enable time xdir to bus 3 13 ns t plz2 3 output disable time xdir to bus high impedance 3 13 ns t phz2 3 output disable time xdir to bus high impedance 3 13 ns t skew 4 skew between outputs 700 ps t ost 5 differential output skew 1500 ps t part 6 part to part skew 500 ps ?? ?? ?? ??
14 ac electrical characteristics (c lock input timing relationships) 1. guaranteed by functional test. symbol parameter vdda vddb min max unit f clock 1 clock frequency 4.5 3.0 3.0 4.5 4.5 3.0 100 90 80 mhz t p 1 clock period 4.5 3.0 3.0 4.5 4.5 3.0 10 11.1 12.5 ns t w 1 pulse duration. clkab or clkba high or low 4.5 3.0 3.0 4.5 4.5 3.0 3.5 5 5 ns t su setup time. a before clkab rising edge or b before clkba rising edge data high 4.5 3.0 3.0 4.5 4.5 3.0 2 3 3 ns data low 4.5 3.0 3.0 4.5 4.5 3.0 1 2 2 t h hold time. bus a after clkab rising edge or bus b after clkba rising edge 4.5 3.0 3.0 4.5 4.5 3.0 1.5 1.5 1.5 ns t plzn t pzhn t pzln t phln t phzn propagation delay input output v ddx v ddx /2 0v t plhn control input 3.3v output normally low enable disable times 3.3v output normally high v ddx v ddx /2 0v v ddx /2 v ddx /2 .7v ddx .2v ddx v ddx /2+0.2 v ddx /2-0.2 .2v ddx + .2v .7v ddx - .2v v oh v ol 0.5v ddx + 0.2 0.5v ddx - 0.2 ac timing waveform s for 3-volt only operation (e.g. v dda = v ddb = 3.3v +/- 0.3v)
15 ac electrical characteris tics (input rise and fall requirements) (all power supply ranges, -55 ? c < t c < +125 ? c) 1. the input rise and fall parameter is guarant eed by characterizati on and is not tested. symbol parameter minimum maximum unit t rise 1 input rise time -- 100 ms t fall 1 input fall time -- 100 ms t h setup and hold timing clock input data input v ddx v ddx /2 0v t su v oh v ol v ddx /2 clock pulse width clock input v ddx v ddx /2 0v t w f clock any input 0.9 * v ddx 0.9 * v ddx 0.1 * v ddx 0.1 * v ddx t rise t fall input rise and fall timing: v ss ac test load or equivalent v ddx 40pf 100ohms v ddx 100ohms dut notes: 1. equivalent test circuit means that du t performance will be co rrelated and remain guaranteed to the applicable test circuit, above, whenever a test platform change necessitates a deviation from the applicable test circuit.
16 package note: 1. all exposed metalized areas must be go ld plated 100 over electroplated nickel underplating 100 microinches thick per mil-prf-38535. 2. lead finish is in acco rdance with mil-prf-38535. 3. seal ring is electrically connected to vss. 4. ceramic is dark alumina. 5. letter designations are to cr oss-referenced to mil-std-1835. 6. lead true position tolerance and coplanarity ar e not measured.
17 ordering information UT54ACS164646S ut54 *** ******* - * * * lead finish: (notes 1 & 2) (a) = solder (c) = gold (x) = factory option (gold or solder) screening: (notes 3 & 4) (c) = hirel temperature (-55 o c to +125 o c) (p) = prototype package type: (u) = 56-lead bottom brazed flatpack part number: (164646s)= 16-bit bidirectional mult ipurpose registered transceiver i/o type: (acs)= cmos comp atible i/o level aeroflex high reliability logic root part number notes: 1. lead finish (a, c, or x) must be specified. 2. if an "x" is specified when ordering, then the part marking will match the lead finish and wi ll be either "a" (solder) or "c " (gold). 3. prototype flow per aeroflex colorado springs manufacturing flows document. tested at 25 o c only. lead finish is gold only. radiation neither tested nor guaranteed. 4. hirel temperature range flow per ae roflex colorado springs manufacturing flow s document. devices are tested at -55 o c, 25 o c and 125 o c. radiation neither tested nor guaranteed.
18 UT54ACS164646S: smd 5962 * 06234 ** * * * lead finish: (notes 1 & 2) (a) = solder (c) = gold (x) = factory option (gold or solder) case outline: (x) = 56-lead ceramic bottom brazed flatpack class designator: (q) = qml class q (v) = qml class v device types: (01) = 16-bit bidirectional mu ltipurpose registered transceiver drawing number: 5962-06234 total dose: (note 3) (r) = 1e5 rads(si) federal stock class designator: no options notes: 1. lead finish (a, c, or x) must be specified. 2. if an "x" is specified when ordering, th en the part marking will match the lead fi nish and will be eith er "a" (solder) or "c " (gold). 3. total dose radiation must be specifie d when ordering. qml-q and qml-v are not available wi thout radiation hardening.
19 colorado toll free: 800-645-8862 fax: 719-594-8468 se and mid-atlantic tel: 321-951-4164 fax: 321-951-4254 international tel: 805-778-9229 fax: 805-778-1980 west coast tel: 949-362-2260 fax: 949-362-2266 northeast tel: 603-888-3975 fax: 603-888-4585 central tel: 719-594-8017 fax: 719-594-8468 www.aeroflex.com info-ams@aeroflex.com our passion for performance is defined by three attributes represented by these three icons: solution-minded, performance-driven and customer-focused aeroflex colorado springs, inc., reserves the right to make changes to any products and services herein at any time without notice. consult aeroflex or an authorized sales representative to verify that the information in this data sheet is current before using this product. aeroflex does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by aeroflex; nor does the purchase, lease, or use of a pr oduct or service from aeroflex convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual rights of aeroflex or of third parties. aeroflex colorado spring s - datasheet definition advanced datasheet - product in development preliminary datasheet - shipping prototype datasheet - shipping qml & reduced hi-rel

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